Summary: We are seeking vertical engineers with RTL or architecture/microarchitecture backgrounds for RISC-V design, particularly with expertise in PCS and FEC. Highlights: 1. Work in several areas of RISC-V design for an advanced technology node 2. Opportunities for advancement 3. Highly learning environment ID: RTL\-4 ###### **Description** We have multiple open positions in our RTL team and we're looking for individuals with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC\-V design for an advanced technology node. Expertise in PCS and FEC is required. We believe in very “vertical” engineers that fully understand the problem to be solved and can take it down to RTL level. What do we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required) ###### **Requirements** * Bachelor's degree in computer science * English C1 * Experience with Timing and Timings Constraints * Experience in Verilog * Experience implementing PCS and FEC algorithms * Experience on Ethernet SERDES PHY and controller integration * Scripting * Experience in ing teams