Physical Implementation Engineer

Description

Summary: Join a highly collaborative team as a Physical Implementation Engineer, taking ownership of physical chip design from implementation to post-silicon validation using cutting-edge technology. Highlights: 1. Work with cutting-edge technology in physical chip design 2. Collaborate with external IP, EDA, and silicon/package vendors 3. Highly collaborative learning environment and career growth opportunities ID: PIE\-1 ###### **Description** We are hiring! Are you passionate about physical chip design and working through complex challenges? We need you! As a Physical Implementation Engineer, you will take ownership of the physical implementation process, from physical chip design to chip production and post\-silicon validation. You will work with cutting\-edge technology, collaborating closely with external IP providers, EDA vendors, and silicon/package vendors to deliver high\-performance SoCs or SiPs for mass production. What do we offer? Flexible work schedules, competitive pay, a highly collaborative learning environment, and opportunities for career growth. Come and join us in the beautiful city of Barcelona! Candies, coffee, and free Spanish lessons included! (Visa sponsorship available if required.) **Key Responsibilities*** Work in the physical implementation process of high\-complexity SoCs using advanced technology nodes. * Collaborate with external IP providers, EDA vendors, and silicon/package vendors for smooth data exchange and communication. * Actively participate in team meetings to provide technical guidance on physical design flow, design for test, and EDA tools and methods. * Moderate design discussions and make decisions quickly and effectively. If you are ready to take on a role in one of the most exciting fields of chip design, apply now! ###### **Requirements** * Master’s or PhD degree in Computer Science, Microelectronics, or Physics. * \[\+] Ability to drive timing and physical design closure * \[\+] Experience with Synopsys PnR ( Fusion Compiler \&/or ICC2 \+ Primetime ) tools * Proven experience with multiple tapeouts of high\-performance SoCs or SiPs for mass production, including reliability and yield optimization. * Demonstrated ability to work in complex SoC or SiP projects * Strong background in high\-speed digital design. * Experience with multi\-chiplet design is a significant advantage. Experience and ability to supervise and mentor* engineers toward achieving same timing and physical verification closure goals ###### SENIOR