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Summary: Join the verification team to ensure the functional correctness and robustness of processor IPs through advanced verification methodologies, contributing to the development and execution of verification environments. Highlights: 1. Develop and execute verification environments based on industry standards 2. Debug verification results and design issues 3. Interact with IP developers to clarify specifications ##### **About SiPearl…** SiPearl is the European fabless designer of sovereign secure high\-performance energy\-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint. In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1\. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France. Incubated within the European Processor Initiative (EPI) consortium and seed\-funded by the European Union, SiPearl employs almost 200 people in : * France (Maisons\-Laffitte, Grenoble, Massy, Sophia Antipolis), * Spain (Barcelona) * and Italy (Bologna) Following a €130 million Series A, the company has launched its Series B round. ##### **Missions** SiPearl is developing the processor dedicated to European supercomputers. In this context, you will join the verification team to ensure the functional correctness and robustness of processor IPs through advanced verification methodologies. Working closely with design engineers, you will contribute to the development and execution of verification environments based on industry standards. In this internship you will: * Understand the IP documentation * Interact with the IP developers to clarify specifications * Plan the different development and verification phases * Develop the verification environment, stimuli, and checkers using UVM * Debug verification results and design issues * Document the verification work and results ##### **What makes you a good match for the role** * Student in the final year of an engineering school or pursuing a Master's degree in electronics, computer engineering, or a related field * Knowledge of **SystemVerilog** for hardware verification * Familiarity with the **UVM (Universal Verification Methodology)** framework * Experience with **Git\-based version control** platforms such as GitLab or GitHub * Comfortable working in a **Linux environment** * Good **written and spoken English** for technical communication **Location \-\> Castelldefels**
